Video monitoring system using daisy chain

ABSTRACT

A video monitoring system using daisy chain is disclosed. A video monitoring system uses daisy chain, which can display more than four divided screens on one display screen with a simple configuration of the video monitoring system by bypassing video signals captured by a plurality of video cameras through many stages.

FIELD OF THE INVENTION

[0001] The present invention relates to a video monitoring system, andmore particularly to a video monitoring system using daisy chain.

DESCRIPTION OF THE RELATED ART

[0002] A conventional video monitoring system is installed in a generalhouse, department store, bank, factory, exhibition hall, etc. to monitorvisitors and prevent a burglary. The conventional video monitoringsystem comprises a plurality of video cameras for capturing videosignals corresponding to objects of monitored areas, a signal processorfor processing video signals captured by video cameras, and a videodisplay device for displaying video images corresponding to theprocessed video signals on one display screen having divided displayscreens.

[0003] The conventional video monitoring system reduces video datacorresponding to video signals captured by four video cameras accordingto a scaling reduction ratio and displays video images corresponding tothe reduced video data on the one display screen containing four dividedscreens. Here, the one display screen containing the four dividedscreens is referred to as a quad screen. According to a quad screencombination, video images corresponding to video signals inputted fromvideo cameras can be displayed on the four divided display screens,eight divided display screens or sixteen divided display screens dividedwithin one full display screen.

[0004] For example, where video signals can be displayed on the sixteendivided screens on the basis of the quad screen combination, four quadunits QUAD1-QUAD4 are configured as shown in FIG. 1. In this case, framememories fm1-fm4 are provided to configure the respective quad screens.A frame memory fm5 and a quad unit QUAD5 are provided to combine quadvideo data from the four quad units QUAD1-QUAD4 to process the combinedquad video data so that sixteen video images corresponding to theprocessed video data are displayed on the sixteen divided screens.

[0005] Therefore, as the number of quad units is increased, the numberof frame memories is increased in order to configure the sixteen dividedscreens. A last stage of the conventional video monitoring systemincludes another quad unit QUAD5 for processing the quad video data fromthe respective quad units in addition to the four quad units QUAD1-QUAD4and another frame memory fm5 for configuring the sixteen divided screensin addition to the frame memories fm1-fm4. There is a problem in that aconfiguration of the conventional video monitoring system is complicatedto configure with more than the four divided screens, and costs forsystem construction are increased.

SUMMARY OF THE INVENTION

[0006] Therefore, the present invention has been made in view of theabove problems, and the present invention provides a video monitoringsystem using daisy chain, which can display more than four dividedscreens on one display screen with a simple configuration of the videomonitoring system by bypassing video signals captured by a plurality ofvideo cameras through many stages.

[0007] The present invention also provides a video monitoring systemusing daisy chain, which can display a plurality of channel video imageson divided screens within one display screen by arbitrarily extendingthe number of divided screens with a single memory.

[0008] In accordance with an aspect of the present invention, a videomonitoring system for configuring and displaying one or more dividedscreens corresponding to one or more video signals captured by one ormore cameras, comprises:

[0009] A/D (Analog/Digital) converters for converting channel videosignals outputted from the video cameras into digital video data;

[0010] one or more slave video signal processors coupled by daisy chainfor reducing the digital video data of each channel outputted from theA/D converters through a video source channel, collecting the digitalvideo data of the video source channel outputted through a first bypasschannel placed at a front stage of a slave video signal processor andthe digital video data of the video source channel outputted through asecond bypass channel placed at the front stage of the slave videosignal processor, and outputting the collected video data to the secondbypass channel;

[0011] a master video signal processor for reducing another digitalvideo data outputted from the A/D converters through the video sourcechannel, recording another digital video data and the digital video dataoutputted from the first bypass channel and the second bypass channelcoupled to a last slave video signal processor among the slave videosignal processors, in a frame memory, and configuring and outputtingvideo data corresponding to multiple channel divided screens; and

[0012] a D/A (Digital/Analog) converter for converting the video datacorresponding to the multiple channel divided screens into analog videosignals and outputting the analog video signals to a video displaydevice.

[0013] The slave video signal processor reduces the digital video dataof the video source channel corresponding to the video signals capturedby each video camera and then outputs the reduced digital video data.The slave video signal processor bypasses the digital video data fromanother slave video signal processor placed at its front stage, therebyoutputting the bypassed digital video data to another slave video signalprocessor placed at its rear stage. The master video signal processormay record the digital video data of the video source channelcorresponding to the video signals captured by respective video camerasand the digital video data bypassed from the slave video signalprocessor placed at its front stage in the frame memory, therebyconfiguring multiple channel divided screens and then outputting theconfigured multiple channel divided screens. Therefore, the videomonitoring system may display the multiple channel divided screens witha simple configuration of the system.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

[0015]FIG. 1 is a view showing a configuration of a conventional videomonitoring system including a plurality of quad units;

[0016]FIG. 2 is a view showing a configuration of a video monitoringsystem using daisy chain in accordance with a first embodiment of thepresent invention;

[0017]FIG. 3 is a block diagram illustrating a video signal processorfor implementing the video monitoring system shown in FIG. 2;

[0018]FIG. 4 is a view explaining a signal transfer procedure when thevideo signal processor shown in FIG. 3 is employed as a slave videosignal processor;

[0019]FIG. 5 is a view explaining a signal transfer procedure when thevideo signal processor shown in FIG. 3 is employed as a master videosignal processor;

[0020]FIG. 6 is a view showing a configuration of a video monitoringsystem using daisy chain in accordance with a second embodiment of thepresent invention; and

[0021]FIG. 7 is a view showing a configuration of a video monitoringsystem using daisy chain in accordance with a third embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

[0022] Now, exemplary embodiments of the present invention will bedescribed in detail with reference to the annexed drawings. In thefollowing description, a detailed description of known functions andconfigurations incorporated herein will be omitted when it may make thesubject matter of the present invention rather unclear.

[0023]FIG. 2 is a view showing a configuration of a video monitoringsystem using daisy chain in accordance with a first embodiment of thepresent invention. In more detail, FIG. 2 is a view showing aconfiguration of a video monitoring system for displaying sixteendivided display screens on a video display device.

[0024] As shown in FIG. 2, the video monitoring system for displayingthe sixteen divided display screens comprises three slave video signalprocessors 18, 20 and 22 and one master video signal processor 24. Theslave video signal processors 18, 20 and 22 and master video signalprocessor 24 will be described below and can be composed of the samecomponents as one another.

[0025] Referring to FIG. 2, A/D (Analog/Digital) converters 10, 12, 14and 16 are coupled to video source channels of the slave video signalprocessors 18, 20 and 22 and master video signal processor 24. The A/D(Analog/Digital) converters 10, 12, 14 and 16 convert channel videosignals outputted from video cameras vc1-vc16 into digital video data.

[0026] The slave video signal processors 18, 20 and 22 reduce thedigital video data of each channel outputted from the A/D converters 10,12 and 14 through the video source channels and then output the reduceddigital video data to a first bypass channel V1, V3 and V5. The slavevideo signal processors 18, 20 and 22 collect the digital video data ofthe video source channels outputted through the first bypass channelN.C., V1 and V3 and the digital video data outputted through a secondbypass channel N.C., V2 and V4 and then output the collected digitalvideo data to the second bypass channel V2, V4 and V6, respectively. Theslave video signal processors 18, 20 and 22 are coupled to one anotherby the daisy chain.

[0027] The master video signal processor 24 reduces the digital videodata outputted from the A/D converters 16 through a video sourcechannel. The master video signal processor 24 records the digital videodata outputted from the first bypass channel V5 and the second bypasschannel V6 coupled to the third slave video signal processor 22, placedat a front stage of the master video signal processor 24 to be describedbelow, in a frame memory 26. The frame memory 26 stores the digitalvideo data for configuring multiple divided display screens. Forreference, a memory controller equipped with the master video signalprocessor 24 controls access to the frame memory 26.

[0028] A D/A (Digital/Analog) converter 28 converts the video datacorresponding to the multiple divided display screens outputted from themaster video signal processor 24 into analog video signals. Forreference, “N.C.” of FIG. 1 is an abbreviation of “No Connection”.Configurations of the slave video signal processors 18, 20 and 22 andmaster video signal processor 24 in the video monitoring system will bedescribed below in detail.

[0029]FIG. 3 is a block diagram illustrating a master or slave videosignal processor for implementing the video monitoring system shown inFIG. 2. In accordance with an embodiment of the present invention, theslave video signal processors 18, 20 and 22 and master video signalprocessor 24 comprise video input controllers 30, horizontal/verticalscalers 32, input buffers 34, a memory controller 36, an output buffer38, a video output controller 40 and a bypass buffer 42, respectively,as shown in FIG. 2.

[0030] The video input controllers 30 extend digital video dataoutputted from the A/D converters 10 coupled to the video sourcechannel, and separate and control horizontal and vertical synchronoussignals. In the video signal processors, the number of video inputcontrollers 30 is the same as the number of A/D converters 10.

[0031] The horizontal/vertical scalers 32 reduce the digital video dataoutputted from the video input controllers 30 in a horizontal directionor/and a vertical direction so that the digital video data can be storedto be displayed on divided display screens. It is clear that thehorizontal/vertical scalers 32 reduce the digital video data byperforming interpolation between adjacent digital video data on thebasis of reduction ratios. The reduction ratios in the horizontal andvertical directions can be varied on the basis of the number of divideddisplay screens to be displayed on a video display device. In theembodiment of the present invention, it is assumed that each slave videosignal processor configures the four divided display screens. In thevideo signal processors, the number of horizontal/vertical scalers 32 isthe same as the number of video cameras.

[0032] The input buffer 34 temporarily stores the video data outputtedfrom the horizontal/vertical scalers 32 and then outputs the video datathrough two channels. One of the two channels is a first bypass channel(Bypass Video Out) and the other channel is needed in the memorycontroller 36 reading the video data.

[0033] The memory controller 36 reads the video data from the inputbuffer 34 on a burst-unit basis and records the read video data at framememory addresses designated channel by channel. The recorded video datais read out so that it can be displayed in real time. In accordance withthe present invention, the slave video signal processors 18, 20 and 22are not directly connected to the memory controller 36 and only themaster video signal processor 24 is directly connected to the memorycontroller 36.

[0034] The output buffer 38 temporarily stores the video datacorresponding to one display screen. The video output controller 40combines supplementary information (including time information, channelinformation, etc.) with the video data of the one display screenoutputted from the output buffer 38 to output the supplementaryinformation and the video data. The video data outputted from the videooutput controller 40 is converted into analog video signals by the D/Aconverter 28 and then the analog video signals are outputted to thevideo display device.

[0035] At last, the bypass buffer 42 receives and temporarily stores thevideo data from a first bypass channel (Bypass Video In) and a secondbypass channel (Bypass Video In) coupled to a slave video signalprocessor placed at its front stage. Then, the bypass buffer 42 outputsthe stored video data to the memory controller 36 and through the secondbypass channel (Bypass Video Out).

[0036] As described above, the slave video signal processors 18, 20 and22 and the master video signal processor 24 in accordance with theembodiment of the present invention can be composed of the samecomponents as one another. However, where the video signal processor isemployed as the slave video signal processor, it can employ only thevideo data outputted through the first bypass channel coupled to anoutput terminal of the input buffer 34.

[0037]FIG. 4 is a view explaining a signal transfer procedure when thevideo signal processor shown in FIG. 3 is employed as a slave videosignal processor. FIG. 5 is a view explaining a signal transferprocedure when the video signal processor shown in FIG. 3 is employed asa master video signal processor.

[0038] In other words, when the video signal processor shown in FIG. 3is employed as the slave video signal processor, the digital video datainputted through the video source channels is transferred to anotherslave video signal processor or the master video signal processor placedat the rear stage of the slave video signal processor through a videoinput controller 30, a horizontal/vertical scaler 32, an input buffer 34and a first bypass channel (Bypass Video Out). Then, the slave videosignal processor collects the digital video data inputted through thefirst bypass channel and a second bypass channel coupled to anotherslave video signal processor placed at its front stage and then outputsit through the second bypass channel. That is, because the slave videosignal processor collects the video data inputted through the videosource channel placed at its front stage, it can be configured as shownin FIG. 4 or FIG. 3.

[0039] The video signal processor shown in FIG. 5 represents the case inwhich the video signal processor shown in FIG. 3 is operated as themaster video signal processor. Video signals outputted from videocameras vc13-vc16 are inputted into a video source channel through A/Dconverters 10. Then, the digital video data inputted through the videosource channels is stored in a frame memory 26 through video inputcontrollers 30, horizontal/vertical scalers 32 and input buffers 34. Thedigital video data outputted through bypass channels V5 and V6, coupledto another slave video signal processor placed at the front stage of thevideo signal processor shown in FIG. 5, is stored in the frame memory 26through a bypass buffer 42 by a frame controller 36. Accordingly, thevideo data stored in the frame memory 26 is controlled by the memorycontroller 36 and externally outputted through an output buffer 38 andvideo output controller 40.

[0040] The operation of the video monitoring system shown in FIG. 2where the slave video signal processors 18, 20 and 22 and the mastervideo signal processor 24 are coupled by the daisy chain will bedescribed below.

[0041] First, video signals captured by four video cameras vc1-vc4 areconverted into digital video data by A/D converters 10. Then, thedigital video data is inputted into a video source channel coupled tothe slave video signal processor 18. Then, the slave video signalprocessor 18 reduces and outputs the video data appropriate to configurethe four divided display screens. The reduced video data is outputted toa first bypass channel V1 through input buffers 34 and then transferredto the slave video signal processor 20. Because no video signalprocessor is connected to the front stage of the slave video signalprocessor 18, there is no data to be transferred to the slave videosignal processor 20 through a second bypass channel V2.

[0042] On the other hand, video signals captured by four video camerasvc5-vc8 are converted into digital video data by A/D converters 12.Then, the digital video data is inputted into a video source channelcoupled to the slave video signal processor 20. Then, the slave videosignal processor 20 reduces and outputs the video data appropriate toconfigure the four divided display screens. The reduced video data isoutputted to the first bypass channel V3 (vc5-vc8) through input buffers34 and then transferred to the slave video signal processor 22. Afterprocessing the video signals captured by the video cameras vc1-vc4, theslave video signal processor 20 receives the digital video data throughthe first bypass channel V1 coupled to the slave video signal processor18 placed at its front stage. The digital video data is transferred tothe second bypass channel V4 (vc1-vc4) through the bypass buffer 42.

[0043] After processing video signals captured by the video camerasvc5-vc8, the slave video signal processor 22 receives the reduced videodata through the first bypass channel V3. Further, after processingvideo signals captured by the video cameras vc1-vc4, the slave videosignal processor 22 receives the reduced video data through the secondbypass channel V4. The video data outputted from two bypass channels V3and V4 is collected in the bypass buffer 42 and then transferred to themaster video signal processor 24 through the second bypass channel V6(vc1-vc8). The digital video data inputted into the video source channelcoupled to the slave video signal processor 22 is transferred to themaster video signal processor 24 through the first bypass channel V5(vc9-vc12) according to the above described operation.

[0044] Accordingly, the bypass buffer 42 within the master video signalprocessor 24 collects the digital video data (vc1-vc12) inputted throughthe first bypass channel V5 and the second bypass channel V6 and thenoutputs it to the memory controller 36. The digital video data of thevideo source channel corresponding to the video signals captured by thevideo cameras vc13-vc16 is reduced and then transferred to the memorycontroller 36. The memory controller 36 within the master video signalprocessor 24 records and stores the digital video data of sixteenchannels at designation addresses of the frame memory 26, therebyconfiguring the sixteen divided display screens. The video datacorresponding to the sixteen divided display screens stored in the framememory 26 is accessed by the memory controller 36 and then transferredto an external D/A converter 28 through the video output controller 40,thereby displaying the sixteen divided display screens on the videodisplay device.

[0045] Because the present invention does not have to configure framememories within every video signal processor for configuring sixteendivided display screens and also does not have to configure anadditional video signal processor for configuring the sixteen divideddisplay screens at a last stage of a video monitoring system, the systemcan be simply configured.

[0046] Further, because video signal processors having the samecomponents as one another are alternatively employed as a slave videosignal processor or master video signal processor, the construction ofthe system can be facilitated and the system can be simply extended orreduced.

[0047] Although the video monitoring system configuring and displayingthe sixteen divided display screens has been described above, it candisplay twelve divided display screens by coupling two slave videosignal processors 18 and 20 and one master video signal processor 24through the daisy chain as shown in FIG. 6. Further, the videomonitoring system can display eight divided display screens by couplingone slave video signal processor 18 and one master video signalprocessor 24 through daisy chain as shown in FIG. 7.

[0048] Therefore, the present invention is not limited to theabove-described embodiments, but the present invention is defined by theclaims which follow, along with their full scope of equivalents.

[0049] Because the present invention does not have to configure framememories within every video signal processor for configuring sixteendivided display screens and also does not have to configure anadditional video signal processor for configuring the sixteen divideddisplay screens at a last stage of a system, the system can be simplyconfigured.

[0050] Further, because video signal processors having the samecomponents as each other are alternatively employed as a slave videosignal processor or master video signal processor, the construction ofthe system can be facilitated and the system can be simply extended orreduced.

What is claimed is:
 1. A video monitoring system for configuring anddisplaying one or more divided screens corresponding to one or morevideo signals captured by one or more cameras, comprising: A/D(Analog/Digital) converters for converting channel video signalsoutputted from the video cameras into digital video data; one or moreslave video signal processors coupled by daisy chain for reducing thedigital video data of each channel outputted from the A/D convertersthrough a video source channel, collecting the digital video data of thevideo source channel outputted through a first bypass channel placed ata front stage of a slave video signal processor and the digital videodata of the video source channel outputted through a second bypasschannel placed at the front stage of the slave video signal processor,and outputting the collected video data to the second bypass channel; amaster video signal processor for reducing another digital video dataoutputted from the A/D converters through the video source channel,recording another digital video data and the digital video dataoutputted from the first bypass channel and the second bypass channelcoupled to a last slave video signal processor among the slave videosignal processors, in a frame memory, and configuring and outputtingvideo data corresponding to multiple channel divided screens; and a D/A(Digital/Analog) converter for converting the video data correspondingto the multiple channel divided screens into analog video signals andoutputting the analog video signals to a video display device.
 2. Thevideo monitoring system of claim 1, wherein each slave video signalprocessor includes: video input controllers for extending the digitalvideo data of the video source channel outputted from each A/D converterand separating and controlling synchronous signals; horizontal/verticalscalers for reducing the digital video data outputted from each videoinput controller in horizontal and vertical directions; input buffersfor temporarily storing the reduced digital video data outputted fromeach horizontal/vertical scaler and outputting the stored digital videodata to the first bypass channel; and a bypass buffer for temporarilystoring the digital video data outputted from the first bypass channeland the second bypass channel placed at the front stage of the slavevideo signal processor and outputting the stored digital video data tothe second bypass channel.
 3. The video monitoring system of claim 2,wherein each slave video signal processor includes: a memory controllerfor reading the video data from each input buffer on a burst-unit basis,recording the read video data at designation addresses of an externalframe memory and reading out the recorded video data so that it can bedisplayed in real time; an output buffer for storing the video data ofone display screen outputted from the memory controller; and a videooutput controller for combining supplementary information with the videodata of the one display screen outputted from the output buffer andoutputting the video data and the supplementary information.
 4. Thevideo monitoring system of claim 1, wherein the master video signalprocessor includes: video input controllers for extending the digitalvideo data of the video source channel outputted from each A/D converterand separating and controlling synchronous signals; horizontal/verticalscalers for reducing the digital video data outputted from each videoinput controller in horizontal and vertical directions; input buffersfor temporarily storing the reduced digital video data outputted fromeach horizontal/vertical scaler and outputting the stored digital videodata through one or more channels; a bypass buffer for temporarilystoring the digital video data outputted from a first bypass channel anda second bypass channel placed at the front stage of the master videosignal processor and outputting the stored digital video data throughone or more channels; a memory controller for reading the video datafrom each input buffer and the bypass buffer on a burst-unit basis,recording the read video data at designation addresses of the framememory, configuring multiple channel divided display screens and readingout the recorded video data so that the configured multiple divideddisplay screens can be displayed in real time; an output buffer forstoring the video data of one display screen outputted from the memorycontroller; and a video output controller for combining supplementaryinformation with the video data of the one display screen outputted fromthe output buffer and outputting the video data and the supplementaryinformation.
 5. The video monitoring system of claim 1, wherein thenumber of the slave video signal processors is one, two or three, andthe one, two or three slave video signal processors are coupled to themaster video signal processor by the daisy chain.